The present disclosure relates generally to forming an integrated circuit device on a substrate and, more particularly, to a chemical mechanical polishing method for fabricating high-k metal gate devices.
Semiconductor device geometries continue to dramatically decrease in size since such devices were first introduced several decades ago. Today's fabrication plants are routinely producing devices having feature dimensions less than 65 nm. However, solving the problems associated with implementing new process and equipment technology while continuing to satisfy device requirements has become more challenging. For example, metal-oxide semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon material has been used due to its thermal resistive properties during high temperature processing, which allows it to be annealed at high temperatures along with source/drain structures.
In some IC designs, there has been a desire to replace the polysilicon gate electrode with a metal gate electrode to improve device performance as feature sizes continue to decrease. A replacement poly gate process (also referred to as a gate last process) may be implemented to address the concerns of high temperature processing on metal materials. In the gate last process, a dummy poly gate is initially formed and the device may continue with processing until deposition of an interlayer dielectric (ILD). The dummy poly gate may then be removed and replaced with a metal gate. However, problems arise when integrating the gate last process with other fabrication processes such as chemical mechanical polishing (CMP) of the ILD layer to expose the dummy poly gate for removal. For example, it may be difficult to control a gate height for devices in various regions of the substrate having different pattern densities.